Multilayering process for stress accommodation in deposited polysilicon
US4742020A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 1, 1985 |
| Grant date | May 3, 1988 |
| Priority date | — |
| Expiry date | Feb 1, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76297
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a process for depositing thick layers of polysilicon which results in less warping or bowing of the wafer unto which the polysilicon is being deposited. This process, referred to as a multilayering deposition process, first consists of the deposition of a continuous, relatively coherent, nucleation layer onto which the multiple layers of polysilicon will be deposited. The multilayering structure is accomplished, according to the invention, by periodically varying one of any selected growth parameter such as, for example, temperature, chemical composition of the polysilicon, or dopant concentration of the polysilicon. The variations are made in a controlled cyclic manner so as to form the multilayered structure. The first deposited nucleation layer undergoes recrystallization after the second deposition cycle as a result of the accommodation to the strain field produced by the multilayering conditions. This recrystallized layer reduces the stress in the polysilicon support structure, thereby reducing the resulting warpage and growth-induced defects in the underlying single crystal substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.