Pradip K. Roy
139Patents
31h-index
87Co-inventors
93Inventor score
Filing activity: Dec 1, 1977 → Feb 12, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US4851370A | Fabricating a semiconductor device with low defect density oxide | Electricity | 270 | Expired |
| US6025280A | Use of SiD.sub.4 for deposition of ultra thin and controllable oxides | Electricity | 152 | Expired |
| US5940736A | Method for forming a high quality ultrathin gate oxide layer | Electricity | 144 | Expired |
| US6246095A | System and method for forming a uniform thin gate oxide layer | Electricity | 132 | Expired |
| US6011404A | System and method for determining near--surface lifetimes and the tunneling field of a dielectric in a semiconductor | Electricity | 96 | Expired |
| US6071808A | Method of passivating copper interconnects in a semiconductor | Electricity | 84 | Expired |
| US5573965A | Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology | Electricity | 80 | Expired |
| US4289794A | Process of preparing gasified candy | Human Necessities | 78 | Expired |
| US6320244A | Integrated circuit device having dual damascene capacitor | Electricity | 78 | Expired |
| US6320238A | Gate structure for integrated circuit fabrication | Electricity | 73 | Expired |
| US5489552A | Multiple layer tungsten deposition process | Electricity | 64 | Expired |
| US6180518A | Method for forming vias in a low dielectric constant material | Electricity | 64 | Expired |
| US6140187A | Process for forming metal oxide semiconductors including an in situ furnace gate stack with varying silicon nitride deposition rate | Emerging Cross-Sectional Technologies | 62 | Expired |
| US5132244A | Growth-modified thermal oxidation for thin oxides | Emerging Cross-Sectional Technologies | 54 | Expired |
| US7704125B2 | Customized polishing pads for CMP and methods of fabrication and use thereof | Performing Operations; Transporting | 52 | Expired |
| US5147820A | Silicide formation on polysilicon | Electricity | 51 | Expired |
| US6265260A | Method for making an integrated circuit capacitor including tantalum pentoxide | Electricity | 48 | Expired |
| US6100587A | Silicon carbide barrier layers for porous low dielectric constant materials | Electricity | 47 | Expired |
| US4742020A | Multilayering process for stress accommodation in deposited polysilicon | Electricity | 44 | Expired |
| US5298436A | Forming a device dielectric on a deposited semiconductor having sub-layers | Electricity | 43 | Expired |
| US6535014B2 | Electrical parameter tester having decoupling means | Physics | 42 | Expired |
| US5523259A | Method of forming metal layers formed as a composite of sub-layers using Ti texture control layer | Electricity | 42 | Expired |
| US7377840B2 | Methods for producing in-situ grooves in chemical mechanical planarization (CMP) pads, and novel CMP pad designs | Performing Operations; Transporting | 41 | Expired |
| US8715035B2 | Customized polishing pads for CMP and methods of fabrication and use thereof | Performing Operations; Transporting | 40 | Active |
| US5960302A | Method of making a dielectric for an integrated circuit | Electricity | 39 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.