CMOS power-on reset circuit
US4746822A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 1986 |
| Grant date | May 24, 1988 |
| Priority date | — |
| Expiry date | Mar 20, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS power-on reset circuit furnishes a reset signal for bringing the components of a circuit to a defined initial state when the common supply voltage is turned on. The output signal of the reset circuit assumes a first constant value as soon as the supply voltage rises above the level required to turn on the pulldown transistor of an initializing inverter in the reset circuit. A delay circuit causes the output signal of the reset circuit to remain at the first constant value for a period of time sufficient to allow the components of the circuit to settle. The output signal of the reset circuit is then forced to a second constant value. The reset circuit is suitable for use with power supply voltages which rise very rapidly or with power supply voltages which rise very slowly (DC sweep).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.