Semiconductor memory with static column decode and page mode addressing capability
US4750839A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1985 |
| Grant date | Jun 14, 1988 |
| Priority date | — |
| Expiry date | Aug 7, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory includes a memory array (10) that is operable to be addressed in either the page mode or the static column decode mode. A column address transparent latch (20) is provided which is controlled to either directly input a column address to a column decoder (26) or to latch the address in response to the generation of the column address strobe. A sequence detect circuit (30) detects the sequence to the row address strobe and the column address strobe to determine whether the page mode or the static column decode mode is generated. The sequence detect circuit (30) generates a Y-enable signal in a circuit (31) for control of the latch (20).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.