Nonvolatile electrically alterable memory and method
US4752912A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 22, 1985 |
| Grant date | Jun 21, 1988 |
| Priority date | — |
| Expiry date | Jul 22, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compact, floating gate, nonvolatile, electrically alterable memory device is fabricated with three layers of polysilicon. In a nonvolatile memory array, each cell is electrically isolated from other cells to eliminate data disturb conditions in nonaddressed cells of the memory array. The memory cell and array is described as including four electrode layers, one of which being formed as a substrate coupling electrode. The cell is also described as being relatively process intolerant. The first electrode layer above the substrate is used to mask the diffusion or implantation of the substrate coupling electrode and other regions in the substrate to form self-aligned active devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.