Split-level CMOS

US4754314A · kind A · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• David B. Scott · Plano, US
• Satwinder S. Malhi · Garland, US

Key dates

• Filing date: Jan 28, 1987
• Grant date: Jun 28, 1988
• Expiry date: Jan 28, 2007

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/01

Abstract

A CMOS device wherein the NMOS devices are bulk devices and the PMOS devices are SOI devices. The PMOS devices are formed with their channel regions in a silicon-on-insulator layer, preferably a laterally recrystallized annealed-polysilicon layer over a silicon dioxide layer.