Switching plane redundancy
US4754434A · kind A · utility
7Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 1985 |
| Grant date | Jun 28, 1988 |
| Priority date | — |
| Expiry date | Aug 28, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/84
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory comprising apparatus for selecting redundant rows of memory cells wherein the addressing of a defective regular row of memory cells coupled to a first set of bit lines results in the selection of a redundant row of memory cells coupled to a second set of bit lines such that signal interference resulting from the simultaneous enablement of two word lines in the memory is avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.