Method of making vertical field effect transistor with plurality of gate input cnnections
US4757029A · kind A · utility
15Cited by
5References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 4, 1987 |
| Grant date | Jul 12, 1988 |
| Priority date | — |
| Expiry date | May 4, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A method of making a vertical field effect transistor (FET) having a plurality of gates which are isolated from each other. Each gate has a contact thereby enabling a single gate which is turned "on" to cause the vertical FET to conduct a current. This configuration allows for a logical "or" function to be implemented in a vertical FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.