Paged memory management unit having variable number of translation table levels
US4763250A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1985 |
| Grant date | Aug 9, 1988 |
| Priority date | — |
| Expiry date | Apr 1, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/652
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a paged memory management unit (PMMU), a translation control (TC) register contains a set of table indexes which define the number of bits of the logical address to be used to access the translation table at the respective levels. The TC register also contains an initial shift field which defines the number of high order bits of the logical address to be discarded before an address translation, and a page size field which defines the number of low order bits of the logical address comprising the page address. Each descriptor in each translation table contains a descriptor type field which defines whether that particular descriptor is a translation descriptor or a pointer descriptor. If a pointer descriptor is encountered at a table level other than the lowest level, the translation table walk is terminated early and the translation performed using that pointer descriptor. In general, a table may occupy either the lower or upper portions of the page in which such table is stored. Each descriptor contains a lower/upper (L/U) bit which defines the relative displacement of the next-lower table relative to the specified table address. If a table is addressed outside the appropriate r…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.