High density electronic package comprising stacked sub-modules
US4764846A · kind A · utility
241Cited by
6References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 5, 1987 |
| Grant date | Aug 16, 1988 |
| Priority date | — |
| Expiry date | Jan 5, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49126
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high density electronic package is disclosed in which a stack of layer-like sub-modules have their edges secured to a stack-carrying substrate, the latter being in a plane perpendicular to the planes in which the sub-modules extend. Each sub-module has a cavity, inside which one or more IC chips are located. Each cavity-providing sub-module may be formed either by securing a rectangular frame to a chip-carrying substrate, or by etching a cavity in a single piece of material. In the latter case, the chips are mounted on the flat surface of one sub-module, and located inside the cavity of the next sub-module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.