Method for making planar vertical channel DMOS structures
US4767722A · kind A · utility
161Cited by
25References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 24, 1986 |
| Grant date | Aug 30, 1988 |
| Priority date | — |
| Expiry date | Mar 24, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
A DMOS power transistor has a vertical gate and a planar top surface. A vertical gate fills a rectangular groove lined with a dielectric material which extends downward so that source and body regions lie on each side of the dielectric groove. Carriers flow vertically between source and body regions and the structure has a flat surface for all masking steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.