Fault-tolerant memory array
US4768169A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 28, 1983 |
| Grant date | Aug 30, 1988 |
| Priority date | — |
| Expiry date | Oct 28, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/187
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array is organized into rows and columns of memory cells, each cell having a configuration which passes current or blocks current depending upon the state of that cell. The array includes sense circuits to sense cell state. In a preferred embodiment of the invention, an address signal sent to the memory array activates two sets of memory cells connected to the same sense lines, and the threshold level of the sense circuits is set above the level which would be sensed for a failed bit, so that a failed bit appears as if unprogrammed or erased. Because each bit is represented by a pair of memory cells, a failed cell in a pair will not affect operation of the functioning cell in the pair or result in error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.