Capacitor-plate bias generator for CMOS DRAM memories
US4769784A · kind A · utility
92Cited by
6References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 19, 1986 |
| Grant date | Sep 6, 1988 |
| Priority date | — |
| Expiry date | Aug 19, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/07
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A capacitor-plate bias generator produces a voltage on the capacitor plate node which consists of a constant voltage plus the sense-level voltage. Consequently, the capacitor-plate node tracks any variations in the sense-level voltage. The constant voltage is 3V.sub.BG, or 3 times the bandgap voltage of silicon. The circuit includes a reference-voltage source which produces the sum of the sense-level voltage and V.sub.BG, and a feedback control circuit for enabling either a charge pump or a charge bleeder to regulate the capacitor-plate voltage at a level above the circuit supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.