On-chip pulse-width control circuit for SRAM memories
US4769791A · kind A · utility
15Cited by
3References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 6, 1986 |
| Grant date | Sep 6, 1988 |
| Priority date | — |
| Expiry date | Aug 6, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The circuit provides one or several banks of capacitors, the capacitors in each bank being identical in size. A single fuse for each bank of capacitors controls the connection of the capacitors to a pulse-width-determining node on each of the ATD (address-transition-detect) pulse generators of the SRAM device. Depending on the position of the fuse in the circuit, the blowing of a single fuse can either add to the capacitance at the ATD nodes or substract from it. Thus the pulse-width of all ATD pulse generators can be adjusted shorter or longer simultaneously by blowing a single fuse only.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.