Memory device employing multilevel storage circuits
US4771404A · kind A · utility
75Cited by
3References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 1985 |
| Grant date | Sep 13, 1988 |
| Priority date | — |
| Expiry date | Aug 28, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/565
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device which employs multilevel memory cells has a basic arrangement in which a write device writes multilevel information corresponding to binary data of plural bits in the memory cells and a readout device outputs binary data of plural bits representing the multilevel information read out of the memory cells. The memory device includes a multilevel detector for detecting the information of the memory cells at one time and reference level generator for generating reference levels therefor, thereby permitting the reduction of the bit area of each memory cell and increased speed during the operation of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.