System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses
US4777587A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 1985 |
| Grant date | Oct 11, 1988 |
| Priority date | — |
| Expiry date | Aug 30, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction processor suitable for use in a reduced instruction-set computer employs an instruction pipeline which performs conditional branching in a single processor cycle. The processor treats a branch condition as a normal instruction operand rather than a special case within a separate condition code register. The condition bit and the branch target address determine which instruction is to be fetched, the branch not taking effect until the next-following instruction is executed. In this manner, no replacement of the instruction which physically follows the branch instruction in the pipeline need be made, and the branch occurs within the single cycle of the pipeline allocated to it. A simple circuit implements this delayed-branch method. A computer incorporating the processor readily executes special-handling techniques for calls on subroutine, interrupts and traps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.