Method of fabrication of MOS transistors having electrodes of metallic silicide
US4780429A · kind A · utility
25Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 12, 1987 |
| Grant date | Oct 25, 1988 |
| Priority date | — |
| Expiry date | Jan 12, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/147
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of fabrication of field-effect transistors having very small dimensions, the gate electrode is formed by a first layer of metallic silicide. Insulating embankments are formed along the lateral edges of the gate and a second layer of metallic silicide is then deposited so as to form the source and drain electrodes. At locations in which the second layer covers the first, planning by planarizing etching is performed so as to produce a structure of flat electrodes in which the gate is separated from the source and drain electrodes by a smaller interval than would be possible in the case of separation by photoetching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.