Process for making structures including E2PROM nonvolatile memory cells with self-aligned layers of silicon and associated transistors

US4780431A · kind A · utility

Assignee

• SGS Microelettronica S.p.A. · IT

Inventors

• Franco Maggioni · Merate, IT
• Carlo Riva · Milano, IT

Key dates

• Filing date: Jul 2, 1987
• Grant date: Oct 25, 1988
• Expiry date: Jul 2, 2007

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/41

Abstract

The process provides for obtaining in the areas intended for the formation of the transistors windows in the intermediate oxide layer between the two silicon layers and, before final etching of the two silicon layers and the intermediate oxide, application of a mask formed in such a manner as to superimpose on the second silicon layer in the transistor areas coverings wider than the corresponding windows of the intermediate oxide layer.