BiMOS biasing circuit
US4780624A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 1987 |
| Grant date | Oct 25, 1988 |
| Priority date | — |
| Expiry date | Apr 15, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/267
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
The circuit comprises a first and a second transistor provided with the sources coupled to one end of a supply voltage and the gates coupled to one another, and a third and fourth transistor provided with the sources coupled to the other end of the supply voltage, the gates coupled to one another, the drains coupled to the respective drains of said first and second transistor, and the gates of the first and of the fourth transistor being furthermore shorted each with its own gate. The coupling between the drains of the first and of the third transistor is constituted by a preset resistor to the ends of which the base and the emitter of a bipolar transistor are coupled having the collector of the bipolar transistor coupled to one end of the supply voltage. The four transistors may be replaced by respective pairs of transistors suitably coupled to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.