Multichip integrated circuit packaging configuration and method
US4783695A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1986 |
| Grant date | Nov 8, 1988 |
| Priority date | — |
| Expiry date | Sep 26, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multichip integrated circuit package comprises a substrate to which is affixed one or more integrated circuit chips having interconnection pads. A polymer film overlying and bridging integrated circuit chips present is provided with a plurality of via openings to accommodate a layer of interconnection metallization which serves to connect various chips and chip pads within the interconnection pads disposed on the chips. A significant advantage of the packaging method and configuration of the present invention is the ability for the polymer film to be removed. This significantly improves testability and effectively provides wafer scale integration circuit packages which are free of problems associated with yield and testability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.