Digital FSK signal demodulator
US4785255A · kind A · utility
14Cited by
11References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1987 |
| Grant date | Nov 15, 1988 |
| Priority date | — |
| Expiry date | Nov 23, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/1566
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A demodulator for a phase coherent frequency shift keyed signal has a master clock which generates a signal having a plurality of pulses during each half of the bit internal of the FSK signal. A detector determines during which master clock pulse within several groups of X number of pulses the most transitions occur in the received signal. Based on the determined clock pulse, samples taken in each of two consecutive half-bit intervals of the FSK signal are selected for comparison to produce the demodulator output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.