Michael Klein
42Patents
7h-index
40Co-inventors
69Inventor score
Filing activity: Jun 17, 1986 → Mar 27, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5153884A | Intelligent network interface circuit | Electricity | 58 | Expired |
| US5970243A | Online programming changes for industrial logic controllers | Physics | 47 | Expired |
| US4785255A | Digital FSK signal demodulator | Electricity | 14 | Expired |
| US5963446A | Extended relay ladder logic for programmable logic controllers | Physics | 12 | Expired |
| US6058333A | Animation of execution history | Emerging Cross-Sectional Technologies | 10 | Expired |
| US10169451B1 | Rapid character substring searching | Electricity | 9 | Active |
| US6275955A | Diagnostic software for facilitating flowchart programming | Emerging Cross-Sectional Technologies | 7 | Expired |
| US8244783B2 | Normalizer shift prediction for log estimate instructions | Physics | 6 | Active |
| US4881229A | Test circuit arrangement for a communication network and test method using same | Electricity | 6 | Expired |
| US8352530B2 | Residue calculation with built-in correction in a floating point unit positioned at different levels using correction values provided by multiplexer | Physics | 6 | Active |
| US4694257A | Phase-coherent demodulation clock and data recovery | Electricity | 5 | Expired |
| US10296294B2 | Multiply-add operations of binary numbers in an arithmetic unit | Physics | 2 | Active |
| US9430190B2 | Fused multiply add pipeline | Physics | 2 | Active |
| US10140090B2 | Computing and summing up multiple products in a single multiplier | Physics | 2 | Active |
| US9513987B2 | Using error correcting codes for parity purposes | Electricity | 1 | Active |
| US9959093B2 | Binary fused multiply-add floating-point calculations | Physics | 1 | Active |
| US10372417B2 | Multiply-add operations of binary numbers in an arithmetic unit | Physics | 1 | Active |
| US9952829B2 | Binary fused multiply-add floating-point calculations | Physics | 0 | Active |
| US10890622B2 | Integrated circuit control latch protection | Physics | 0 | Active |
| US10983159B2 | Method and apparatus for wiring multiple technology evaluation circuits | Physics | 0 | Active |
| US11175890B2 | Hexadecimal exponent alignment for binary floating point unit | Physics | 0 | Active |
| US9734126B1 | Post-silicon configurable instruction behavior based on input operands | Physics | 0 | Active |
| US9529664B2 | Using error correcting codes for parity purposes | Electricity | 0 | Active |
| US11861325B2 | Repurposed hexadecimal floating point data path | Physics | 0 | Active |
| US11159183B2 | Residue checking of entire normalizer output of an extended result | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.