Processor to peripheral interface for asynchronous or synchronous applications
US4785469A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1987 |
| Grant date | Nov 15, 1988 |
| Priority date | — |
| Expiry date | Feb 12, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed herein an interface for a peripheral to allow the peripheral to communicate with either synchronous or asynchronous systems. The interface includes a series of flip-flops coupled in a chain to take the combined data strobe and chip select signals from an asynchronous system such as a microprocessor and synchronize the combined signal with the peripheral clock and convert the signal to a pulse. This pulse then emulates the instruction enable pulse received from synchronous microprogrammed systems. If the peripheral is operating in a synchronous sytem, the instruction enable signal from the system is gated through a multiplexer controlled by a mode signal which indicates which mode is active so as to act as the peripheral instruction enable signal. An AND gate gates one bit of the instruction bus with the ANDed chip select and data strobe signals to create a read/write control signal for internal use in controlling the data bus drivers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.