Method of fabricating field-effect transistor utilizing improved gate sidewall spacers
US4786609A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 5, 1987 |
| Grant date | Nov 22, 1988 |
| Priority date | — |
| Expiry date | Oct 5, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Gate sidewall spacers are created by a two-step procedure in fabricating a field-effect transistor using a protective material such as silicon nitride to prevent gate-electrode oxidation. In the first step, a layer (32) of insulating material is conformally deposited and then substantially removed except for small spacer portions (34) adjoining the sidewalls of a doped non-monocrystalline semiconductor layer (20A) destined to become the gate electrode (36). The second step consists of performing an oxidizing heat treatment to increase the thickness of the spacer portions. No significant gate dielectric encroachment occurs. Also, the spacers achieve a profile that substantially avoids electrical shorts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.