Process for formation of shallow silicided junctions
US4788160A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1987 |
| Grant date | Nov 29, 1988 |
| Priority date | — |
| Expiry date | Mar 31, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/923
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming shallow silicided junctions includes the step of sputtering a layer of titanium (28) over a moat region to cover a gate electrode (18) and a sidewall oxide (22) formed on the sidewalls of the gate electrode (18). The titanium is reacted with exposed silicon regions (24) and (26) to form silicide layers (30) and (32) and then dopant impurities are implanted into the substrate (10) prior to stripping the unreacted titanium. The unreacted titanium (36), (38), or (40) functions as a mask to both offset the implanted regions from the channel region (20) under the gate electrode (18) and also to prevent impurities from entering the substrate at regions outside the defined moat region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.