CMOS row decoder circuit for use in row and column addressing
US4788457A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 1987 |
| Grant date | Nov 29, 1988 |
| Priority date | — |
| Expiry date | Sep 9, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS row decoder circuit in which a row decoder for selecting a single word line from a memory cell array and a column decoder for selecting a single bit line can use in common an internal address signal transmission line. The row decoder circuit comprises a series of MOSFETs of a first conductivity type which is turned on or off in response to address signals selected from external address signals, a second MOSFET of a second conductivity type provided between a power supply potential and the series of MOSFETs and having a gate receiving a first timing signal for providing decoding timing of the address signals, a third MOSFET of the first conductivity type provided between the series of MOSFETs and the second MOSFET and having a gate receiving a first operation timing signal, a fourth MOSFET which is turned on or off in response to a second operation timing signal for transmitting the potential of a node of the second MOSFET and the third MOSFET, and a fifth MOSFET having a gate receiving an output of the fourth MOSFET for transmitting a word line driving signal to a corresponding word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.