Clock voltage supply

US4788670A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Hermann Hofmann · Solms, DE
• David L. Johnson · Pleasanton, US
• Werner Schirl · Wendelstein, DE
• Hans-Peter Troendle · Forchheim, DE

Key dates

• Filing date: Aug 18, 1987
• Grant date: Nov 29, 1988
• Expiry date: Aug 18, 2007

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F1/04
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A clock voltage supply for electronic control circuits such as a computer system for generating four clock signals which are synchronous as to frequency and phase. When n=4, the clock signals are generated with the help of four PLL clocks. So that the four clock signals can continue to appear even if one of the four clocks is malfunctioning, the clock signals of the four clocks are supplied to four (3:4) voters from whose outputs the clock signals are then supplied. Since each voter circuit brings about a certain delay time, which significantly limits the frequency of the clock signals, a delay element is connected downstream to each of the voter outputs respectively. The delay time of the respective delay element, plus the delay time of the respective voter connected therewith, is an integral multiple of the period of the intended clock frequency. For PLL control, the output of each delay element gives the nominal phase position and the output of each clock gives the actual phase position.