Test device for a combinatorial logic circuit and integrated circuit including such a device
US4789821A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 1987 |
| Grant date | Dec 6, 1988 |
| Priority date | — |
| Expiry date | Jan 8, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318321
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
This device and method for testing a combinative logic circuit (4), includes on the one hand a circuit generating test sequences (30) for applying test logic signals to N inputs of the combinative logic circuit and, on the other hand, an output circuit (5) to analyze the output signals of the combinative logic circuit. These test sequences are successively applied to each of the N inputs (E1, E2, E3 and E4) so that an alternating series, at least twice, of logic "1"'s and of logic "0"'s while a word of N-1 bits is applied to the other inputs to ensure the transmission of the said alternating series to the output of the combinative logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.