Programmable array logic cell
US4789951A · kind A · utility
80Cited by
4References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 1986 |
| Grant date | Dec 6, 1988 |
| Priority date | — |
| Expiry date | May 16, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/037
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable array logic cell 60 including a sum-of-products array having a single OR gate 70 for providing a sum signal, and including an XOR gate 80 for combining the sum signal with a product signal provided by an AND gate 78 from selected array input and/or feedback signals. The product signal can be the previous state output signal Q for a JK flip flop configuration, or a forced high or low signal for other configurations for programmable output signal polarity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.