Process for making a hermetic low cost pin grid array package
US4791075A · kind A · utility
70Cited by
6References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 5, 1987 |
| Grant date | Dec 13, 1988 |
| Priority date | — |
| Expiry date | Oct 5, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for making hermetic, low cost pin grid array (PGA) semiconductor die packages. The process involves die bonding a semiconductor die or integrated circuit chip to a substrate having an interconnect or metallization pattern thereon. The die is electrically connected to the pattern and then the die and the inner bonds are hermetically sealed inside a cap that is smaller than the substrate so that the ends of the metallization pattern are exposed. The leads are then electrically connected, such as by solder or other technique to the exposed ends of the pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.