Memory with redundancy and predecoded signals
US4791615A · kind A · utility
30Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1986 |
| Grant date | Dec 13, 1988 |
| Priority date | — |
| Expiry date | Dec 22, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory has an address buffer which receives a row address and a column address and outputs these buffered address signals to a predecoder. A row decoder and column decoder use predecoded signals provided by the predecoder to select a row and a column from a main array. A redundant row is provided to replace a defective row from the main array. A programmable redundant decoder is programmable to select the redundant row in response to the predecoder signals which select the defective row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.