Digital computer with cache capable of concurrently handling multiple accesses from parallel processors
US4794521A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1985 |
| Grant date | Dec 27, 1988 |
| Priority date | — |
| Expiry date | Jul 22, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0859
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory capable of concurrently accepting and working on completion of more than one cache access from a plurality of processors connected in parallel. Current accesses to the cache are handled by current-access-completion circuitry which determines whether the current access is capable of immediate completion and either completes the access immediately if so capable or transfers the access to pending-access-completion circuitry if not so capable. The latter circuitry works on completion of pending accesses; it determines and stores for each pending access status information prescribing the steps required to complete the access and redetermines that status information as conditions change. In working on completion of current and pending accesses, the addresses of the accesses are compared to those of memory accesses in progress on the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.