Power-on reset circuit for MOS logic devices
US4797584A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1987 |
| Grant date | Jan 10, 1989 |
| Priority date | — |
| Expiry date | Feb 13, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The power-on reset circuit is adapted to automatically provide a voltage pulse as a positive supply voltage is applied. It essentially comprises: PA1 (a) a voltage divider adapted for supplying a reference voltage, comprised of a first and a second series arranged transistors of the normally conducting type, with one end coupled to ground and the opposite end coupled to the supply voltage; PA1 (b) a bistable circuit comprised of a third and fourth transistors, of the normally non-conducting type (or enhancement type) having their respective gates and drains cross coupled, the drain of said first transistor being coupled to the connection point of the two transistors of said voltage divider through de-coupling means, and the drain of said fourth transistor being coupled on a side to said supply voltage through a fifth transistor which is normally coupled as a diode, and, on the other side, being coupled to the ground through resistance means; and PA1 (c) an end stage comprised of a normally locked sixth transistor having the source coupled to the ground and the gate coupled to the drain of said fourth transistor and a seventh transistor having the source coupled to the drain of said…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.