Semiconductor memory device
US4797717A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1987 |
| Grant date | Jan 10, 1989 |
| Priority date | — |
| Expiry date | Apr 17, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
Abstract
Each of the memory cells in a SRAM includes two driver MOS transistors, two transfer gate MOS transistors and two load resistances. The gate electrode layers of the MOS transistors are formed from a first-level conductive layer provided on the surface of a semiconductor substrate. The source regions of the two driver MOS transistors in each memory cell are connected in common and further connected to a ground potential point through a second-level conductive layer. The two load resistances in each memory cell are formed from a third-level high-resistance material layer. The second-level conductive layer is formed from a low-resistance material layer. Thus the resistance of the sources of the two driver MOS transistors is lowered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.