Fast flush for a first-in first-out memory
US4802122A · kind A · utility
35Cited by
3References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1987 |
| Grant date | Jan 31, 1989 |
| Priority date | — |
| Expiry date | Apr 28, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory circuit including a write bit-line for writing data into a memory cell, and a read bit-line for reading data from the cell, a transistor is included, connected with the write bit-line and the read bit-line, so that when a fast flush signal is applied to the gate of that transistor, direct connection is made between the write bit-line and read bit-line, so that data is written into the cell, but can be read simultaneously from the read bit-line, reducing the fall-through delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.