Analog phase locked loop
US4803705A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 1987 |
| Grant date | Feb 7, 1989 |
| Priority date | — |
| Expiry date | Aug 19, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A phase locked loop for synchronizing a local digital signal with an incoming data signal is described. Parallel phase and frequency detectors compare the local and incoming signals and generate control pulse signals for controlling the frequency of a voltage controlled oscillator which generates the local digital signal. Logic circuitry is included in both the phase and frequency detectors for adjusting the generated control pulse signals in the event of detection of elongated pulse widths of the incoming data signal, indicating one of either an absence of incoming data signal or a bipolar violation in the event the data signals are ASI encoded. The phase locked loop is characterized by quick pull-in time, large pull-in frequency range, accurate clocking and low cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.