Peter B. Gillingham
141Patents
29h-index
56Co-inventors
93Inventor score
Filing activity: Oct 3, 1985 → Dec 1, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6442644B1 | Memory system having synchronous-link DRAM (SLDRAM) devices and controller | Emerging Cross-Sectional Technologies | 382 | Expired |
| US6510503B2 | High bandwidth memory interface | Emerging Cross-Sectional Technologies | 294 | Expired |
| US5694143A | Single chip frame buffer and graphics accelerator | Physics | 185 | Expired |
| US5283761A | Method of multi-level storage in DRAM | Physics | 171 | Expired |
| US6236581A | High voltage boosted word line supply charge pump and regulator for DRAM | Electricity | 127 | Expired |
| US6088774A | Read/write timing for maximum utilization of bidirectional read/write bus | Physics | 107 | Expired |
| US5796673A | Delay locked loop implementation in a synchronous dynamic random access memory | Electricity | 101 | Expired |
| US6779097B2 | High bandwidth memory interface | Emerging Cross-Sectional Technologies | 78 | Expired |
| US6657919B2 | Delayed locked loop implementation in a synchronous dynamic random access memory | Electricity | 74 | Expired |
| US6657918B2 | Delayed locked loop implementation in a synchronous dynamic random access memory | Electricity | 72 | Expired |
| US6992950B2 | Delay locked loop implementation in a synchronous dynamic random access memory | Electricity | 71 | Expired |
| US7299330B2 | High bandwidth memory interface | Emerging Cross-Sectional Technologies | 71 | Expired |
| US6182257A | BIST memory test system | Physics | 67 | Expired |
| US4803705A | Analog phase locked loop | Electricity | 62 | Expired |
| US6584003B1 | Low power content addressable memory architecture | Physics | 52 | Expired |
| US5267201A | High voltage boosted word line supply charge pump regulator for DRAM | Electricity | 48 | Expired |
| US5600598A | Memory cell and wordline driver for embedded DRAM in ASIC process | Physics | 48 | Expired |
| US5414662A | Dynamic random access memory using imperfect isolating transistors | Physics | 47 | Expired |
| US6320777A | Dynamic content addressable memory cell | Physics | 45 | Expired |
| US6708250B2 | Circuit and method for performing variable width searches in a content addressable memory | Physics | 44 | Expired |
| US5144223A | Bandgap voltage generator | Emerging Cross-Sectional Technologies | 43 | Expired |
| US5694355A | Memory cell and wordline driver for embedded DRAM in ASIC process | Physics | 39 | Expired |
| US6768659B2 | Circuit and method for reducing power usage in a content addressable memory | Physics | 38 | Expired |
| US5854763A | Integrated circuit with non-binary decoding and data access | Physics | 38 | Expired |
| US6067272A | Delayed locked loop implementation in a synchronous dynamic random access memory | Electricity | 34 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.