High impendance-coupled CMOS SRAM for improved single event immunity
US4805148A · kind A · utility
Inventors
Key dates
| Filing date | Nov 22, 1985 |
| Grant date | Feb 14, 1989 |
| Priority date | — |
| Expiry date | Nov 22, 2005 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/906
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CMOS SRAM exhibiting a high level of immunity to single event upset errors, such as caused by ionizing radiation, is disclosed. In CMOS SRAM cells with small feature sizes, single event errors result from ion interactions with transistor drains on the side of a cell holding a low voltage. The configuration of the cell presents a high impedance between these low voltage drains and the low voltage gate on the opposite side of the cell, while presenting a high impedance between corresponding components with high voltages. The SRAM cell is protected from single event errors while minimizing the increase in switching speed which accompanies any increase in internal cell impedance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.