Nonvolatile semiconductor memory device
US4805151A · kind A · utility
42Cited by
0References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 11, 1987 |
| Grant date | Feb 14, 1989 |
| Priority date | — |
| Expiry date | May 11, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/344
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an EEPROM capable of writing data in a page mode, an output portion of a Y decoder is provided with a column latch circuit for storing a Y gate line selected by a Y decoder at the time of writing data. The column latch circuit activates the Y gate line selected in response to the stored information at the cycle of verifying erasing and connects a memory cell connected to the Y gate line to a data output line. Thus, it can be determined whether the erased memory cell was surely erased or not in a page mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.