IC which eliminates support bias influence on dielectrically isolated components
US4807012A · kind A · utility
19Cited by
10References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 18, 1985 |
| Grant date | Feb 21, 1989 |
| Priority date | — |
| Expiry date | Sep 18, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/74
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In integrated circuits having device islands separated laterally by support to polycrystalline regions and a dielectric layer, a shield layer is provided along the side walls at the dielectric layer having an impurity concentration sufficiently greater than the island's impurity concentration to eliminate support bias influence without seriously affecting the PN junction in the island. The shield impurity concentration is less than the region forming a PN junction with the island and preferably is below 1.times.10.sup.13 ions/cm.sup.2 and a peak impurity concentration less than 5.times.10.sup.16 ions/cm.sup.3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.