Memory address mapping mechanism
US4807119A · kind A · utility
4Cited by
4References
1Claims
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Assignee
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Key dates
| Filing date | Jul 24, 1986 |
| Grant date | Feb 21, 1989 |
| Priority date | — |
| Expiry date | Jul 24, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0653
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory address mapping mechanism includes a flip-flop for latching a signal (PROT) representing the real or protective virtual address mode. AN output signal from the flip-flop is supplied to an address decoder. In either the real or protective virtual address mode, the address decoder receives the address signal from a microprocessor and the signal (PROT) from the flip-flop, decodes the address signal so as to obtain a continuous memory address space, and outputs a memory address selection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.