Redundancy for a block-architecture memory
US4807191A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 4, 1988 |
| Grant date | Feb 21, 1989 |
| Priority date | — |
| Expiry date | Jan 4, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A block architecture memory has two stacks of memory blocks. Between the two stacks are blocks of sense amplifiers. Each block of sense amplifiers is coupled to a memory block in each of the stacks of memory blocks via local data lines. Located at the bottom of each stack of memory blocks is a redundant block of columns of memory cells. There is a redundant sense amplifier located between and coupled to the redundant blocks of columns via local data lines. The redundant sense amplifier is also coupled to a redundant global data line. An input/output multiplexer is coupled to all of the global data lines. The multiplexer provides and receives external data. If one of the redundant columns is to replace a defective column for a particular address, then the redundant global data line carries data which corresponds to the external data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.