Seimiconductor memory device having sub bit lines
US4807194A · kind A · utility
25Cited by
1References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 20, 1987 |
| Grant date | Feb 21, 1989 |
| Priority date | — |
| Expiry date | Apr 20, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory includes a memory cell array, sense amplifiers disposed at both sides of the memory cell array, and sub bit lines coupled to the sense amplifiers. The sub bit lines may be coupled to data busses through middle amplifiers. By use of such a memory architecture, a higher integration of a DRAM can be realized. Also, the handling of super large bit data, i.e. more than 1024 bits becomes possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.