Memory input buffer with hysteresis and dc margin
US4807198A · kind A · utility
6Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1987 |
| Grant date | Feb 21, 1989 |
| Priority date | — |
| Expiry date | Dec 28, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory has input buffer circuit which provides high immunity to problems associated with address float while providing high speed for both decoder selection and for transition detection. The input buffer circuit includes a pair of input NOR gates which provides for independent signal paths to a cross-coupled latch. Independent hysteresis circuits are provided to each signal path between the two NOR gates and the cross-coupled latch. This allows for independently selecting the amount of dc margin and hysteresis so that the use of hysteresis does not adversely effect dc margin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.