Method of forming completely metallized via holes in semiconductors
US4808273A · kind A · utility
80Cited by
11References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 10, 1988 |
| Grant date | Feb 28, 1989 |
| Priority date | — |
| Expiry date | May 10, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76898
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for forming completely metallized via holes in semiconductor wafers. Metal pads are formed on one face of a semiconductor wafer together with a conductive interconnecting network. An insulating layer is then deposited to cover this face of the wafer. Holes are etched in the opposite face of the wafer up to and exposing a portion of the metal pads. The via holes are then completely filled with metal by means of electroplating, using the metal pads as a cathode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.