Simon S. Chan
92Patents
16h-index
92Co-inventors
87Inventor score
Filing activity: May 10, 1988 → Jun 18, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US4978639A | Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips | Emerging Cross-Sectional Technologies | 106 | Expired |
| US4842699A | Method of selective via-hole and heat sink plating using a metal mask | Electricity | 94 | Expired |
| US6124203A | Method for forming conformal barrier layers | Electricity | 87 | Expired |
| US4808273A | Method of forming completely metallized via holes in semiconductors | Electricity | 80 | Expired |
| US5670828A | Tunneling technology for reducing intra-conductive layer capacitance | Electricity | 63 | Expired |
| US6143672A | Method of reducing metal voidings in 0.25 .mu.m AL interconnect | Electricity | 57 | Expired |
| US6060380A | Antireflective siliconoxynitride hardmask layer used during etching processes in integrated circuit fabrication | Electricity | 49 | Expired |
| US6043153A | Method for reducing electromigration in a copper interconnect | Electricity | 48 | Expired |
| US6259115A | Dummy patterning for semiconductor manufacturing processes | Electricity | 38 | Expired |
| US6312874A | Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials | Electricity | 38 | Expired |
| US5288660A | Method for forming self-aligned t-shaped transistor electrode | Electricity | 32 | Expired |
| US6867130B1 | Enhanced silicidation of polysilicon gate electrodes | Electricity | 31 | Expired |
| US6642119B1 | Silicide MOSFET architecture and method of manufacture | Emerging Cross-Sectional Technologies | 29 | Expired |
| US6472317B1 | Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers | Electricity | 24 | Expired |
| US6156643A | Method of forming a dual damascene trench and borderless via structure | Electricity | 22 | Expired |
| US6518173B1 | Method for avoiding fluorine contamination of copper interconnects | Electricity | 18 | Expired |
| US6093635A | High integrity borderless vias with HSQ gap filled patterned conductive layers | Emerging Cross-Sectional Technologies | 16 | Expired |
| US5861677A | Low RC interconnection | Electricity | 15 | Expired |
| US6670259B1 | Inert atom implantation method for SOI gettering | Electricity | 15 | Expired |
| US5994778A | Surface treatment of low-k SiOF to prevent metal interaction | Emerging Cross-Sectional Technologies | 14 | Expired |
| US6624476B1 | Semiconductor-on-insulator (SOI) substrate having selective dopant implant in insulator layer and method of fabricating | Electricity | 14 | Expired |
| US6967160B1 | Method of manufacturing semiconductor device having nickel silicide with reduced interface roughness | Electricity | 14 | Expired |
| US5760480A | Low RC interconnection | Electricity | 14 | Expired |
| US6291339A | Bilayer interlayer dielectric having a substantially uniform composite interlayer dielectric constant over pattern features of varying density and method of making the same | Electricity | 11 | Expired |
| US5814560A | Metallization sidewall passivation technology for deep sub-half micrometer IC applications | Electricity | 11 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.