JMOS transistor utilizing polysilicon sinks
US4811063A · kind A · utility
1Cited by
8References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 1987 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | Oct 20, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/637
Abstract
JMOS depletion mode transistors include back-to-back junctions in the doped polysilicon layer that serves as the gate. The polysilicon layer includes a first region of the same conductivity type as the channel in contact with the channel, and a second region, of the same conductivity type as the channel and to which the gate potential is applied, spaced apart by a region of the opposite conductivity type that serves as a sink for minority carriers in the channel. Both buried oxide layer and recessed gate JMOS transistors are included.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.