Retiming circuit for pulse signals, particularly for microprocessor peripherals
US4811282A · kind A · utility
40Cited by
3References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 18, 1986 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | Dec 18, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/005
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital retiming circuit for synchronizing a pulse signal with a local clock aligns incoming pulse signals with the local clock using a fully digital technique. The incoming signal is stored in a storage circuit which is disabled until the pulse signal has gone low before rising again. The output of the storage circuit is used to trigger a flip-flop, whose output is converted into a signal aligned with the local clock by means of a cascade of inverters and transfer gates enabled by the local clock. A trigger circuit resets the flip-flop in step with the clock whenever the incoming pulse signal is low.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.