Data integrity verifying circuit for electrically erasable and programmable read only memory (EEPROM)
US4811294A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 1986 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | Jun 20, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An EEPROM provided with a write/erase checking circuit comprising, a data detector for determining whether one byte in an input data contains a "0" (representing that a memory cell is not in an erase state); an address latch circuit and a data latch circuit which latch the address and the input data, respectively, responsive to a detection signal from the data detector; a data read circuit which selects the memory cells according to the address stored in the address latch circuit and reads the data out of the memory cells at the data write checking; and a comparator which compares the data from the data read circuit with the data stored in the data latch circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.