Method for digital slope control of output signals of power amplifiers in semiconductor chips
US4815113A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 1987 |
| Grant date | Mar 21, 1989 |
| Priority date | — |
| Expiry date | Oct 20, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018557
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for the digital slope control of the output signals of power amplifiers, as well as a power amplifier suitable for carrying out the method as described. One way of representing the actual slope value is via the number of clock pulses applied to a counter during a measuring interval which depends in its duration on the slope. Such a measuring interval is produced by applying the pulses of a ring oscillator containing one of the power amplifiers to another counter until the overflow of the latter. Another mode of representing the actual slope value consists in counting the number of pulses of the ring oscillator during a measuring interval of predetermined duration. Actual and nominal values of the slope are compared. The results of this comparison change the contents of a left/right-shift register. Its parallel outputs influence, via control lines, control inputs of the power amplifiers in order to alter their slope by switching on or off output transistors arranged in parallel with respect to their switching paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.